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ICPADS
2006
IEEE
16 years 21 days ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
DSVIS
2008
Springer
15 years 8 months ago
A Middleware for Seamless Use of Multiple Displays
Abstract. Current multi-display environments (MDEs) can be composed of displays with different characteristics (e.g. resolution, size) located in any position and at different angl...
Satoshi Sakurai, Yuichi Itoh, Yoshifumi Kitamura, ...
ICASSP
2011
IEEE
14 years 10 months ago
Fast estimation of the state of the power grid using synchronized phasor measurements
—Both the communication limitation and the measurement properties based algorithm become the bottleneck of enhancing the traditional power system state estimation speed. The avai...
Tao Yang, Anjan Bose
SPAA
1997
ACM
15 years 11 months ago
Pipelining with Futures
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
Guy E. Blelloch, Margaret Reid-Miller
EUROPAR
2000
Springer
15 years 10 months ago
Design and Evaluation of a Compiler-Directed Collective I/O Technique
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
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