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FPL
2010
Springer
148views Hardware» more  FPL 2010»
15 years 4 months ago
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...
Muhammad Shafiq, Miquel Pericàs, Nacho Nava...
PPL
2007
86views more  PPL 2007»
15 years 5 months ago
Failure-Sensitive Analysis of Parallel Algorithms with Controlled Memory Access Concurrency
ract problem of using P failure-prone processors to cooperatively update all locations of an N-element shared array is called Write-All. Solutions to Write-All can be used iterati...
Chryssis Georgiou, Alexander Russell, Alexander A....
SPAA
2005
ACM
15 years 11 months ago
Efficient algorithms for verifying memory consistency
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...
Chaiyasit Manovit, Sudheendra Hangal
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 10 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
POPL
2009
ACM
16 years 6 months ago
The semantics of x86-CC multiprocessor machine code
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, t...
Susmit Sarkar, Peter Sewell, Francesco Zappa Narde...