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IPPS
2005
IEEE
16 years 5 days ago
Stream PRAM
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
Darrell R. Ulm, Michael Scherger
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
16 years 5 days ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
ISM
2005
IEEE
159views Multimedia» more  ISM 2005»
16 years 5 days ago
Avatar-centric Risk Evaluation
Hazard detection and prevention of natural and manmade disasters at critical civil infrastructure is becoming increasingly important. Recent events, such as earthquakes and terror...
Maria-Cruz Villa-Uriol, Falko Kuester, Oscar Garc&...
ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
16 years 5 days ago
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
Hao Yu, Lei He
ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
16 years 5 days ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
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