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DFT
2006
IEEE
143views VLSI» more  DFT 2006»
16 years 20 days ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
GLOBECOM
2006
IEEE
16 years 19 days ago
Optimal Routing Between Alternate Paths With Different Network Transit Delays
— We consider the path-determination problem in Internet core routers that distribute flows across alternate paths leading to the same destination. We assume that the remainder ...
Essia Hamouda Elhafsi, Mart Molle
GLOBECOM
2006
IEEE
16 years 19 days ago
Implementation of a Coded Modulation for Deep Space Optical Communications
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
Michael K. Cheng, Bruce E. Moision, Jon Hamkins, M...
HPDC
2006
IEEE
16 years 19 days ago
ALPS: An Application-Level Proportional-Share Scheduler
ALPS is a per-application user-level proportional-share scheduler that operates with low overhead and without any special kernel support. ALPS is useful to a range of applications...
Travis Newhouse, Joseph Pasquale
ICAT
2006
IEEE
16 years 19 days ago
The Design and Implementation of the Cicada Wireless Sensor Network Indoor Localization System
The wireless sensor network based localization system—Cicada is designed to support the locationawareness in indoor environment. The system is based on TDOA (time difference of ...
Wenfeng Jiang, Yu Chen, Yuanchun Shi, Yunfeng Sun
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