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ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
16 years 3 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
ICC
2007
IEEE
133views Communications» more  ICC 2007»
16 years 21 days ago
Downlink TCP Performance Under Cross Layer Rate and Power Allocation in Infrastructure TH-PPM UWB Networks
Ultra wideband (UWB) systems are currently an important wireless infrastructure for efficient shortrange communications. To improve the system efficiency while guaranteeing the ra...
Yang Liu, Yu-Kwong Kwok, Jiangzhou Wang
HICSS
2003
IEEE
127views Biometrics» more  HICSS 2003»
15 years 11 months ago
SME E-Procurement Adoption in Hong Kong - The Roles of Power, Trust and Value
The objective of this research is to test a model of electronic procurement (e-procurement) adoption behavior by Small- to Medium-sized Enterprises (SME). We investigate the pheno...
Joyce K. Y. Chan, Matthew K. O. Lee
ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
15 years 10 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 10 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu