This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
With reference to digital input power amplifier for automotive audio applications, the paper presents an exhaustive exploration of the huge mixed-signal space to find optimal trad...
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
Chika O. Nwankpa, A. S. Deese, Qingyan Liu, Aaron ...
Abstract— We consider the problem of power controlled minimum frame length scheduling for TDMA wireless networks. Given a set of one-hop transmission requests, our objective is t...
Arindam Kumar Das, Robert J. Marks II, Payman Arab...
This paper presents a design and optimization technique for the Multiple Restricted Multiplication problem [1]. This refers to a situation where a single variable is multiplied by...
Nalin Sidahao, George A. Constantinides, Peter Y. ...