5215 search results - page 141 / 1043 » A model of normative power |
124
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
163
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
172
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ISCAS
2007
IEEE
16 years 19 days ago
2007
IEEE
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
149
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DATE
2005
IEEE
15 years 12 months ago
2005
IEEE
This paper presents a scheme to combine memory and power management for achieving better energy reduction. Our method periodically adjusts the size of physical memory and the time...
167
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SBCCI
2005
ACM
15 years 12 months ago
2005
ACM
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...