5215 search results - page 134 / 1043 » A model of normative power |
157
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PCRCW
1997
Springer
15 years 10 months ago
1997
Springer
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As...
202
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POPL
2009
ACM
16 years 1 months ago
2009
ACM
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets...
142
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ISCAS
2006
IEEE
16 years 11 days ago
2006
IEEE
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
142
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
169
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GLVLSI
2007
IEEE
15 years 8 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...