o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
A delay abstraction of a combinational module is a compact representation of the delay information of the module, which carries effective pin-to-pin delay for each primary-input/pr...
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...