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IPPS
2006
IEEE
16 years 23 days ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
IPPS
2006
IEEE
16 years 23 days ago
Broadcasting and routing in faulty mesh networks
— Broadcasting is a data communication task in which one processor sends the same message to all other processors. Routing is a task where a source processor sends a message to a...
Milos Stojmenovic, Amiya Nayak
IPPS
2006
IEEE
16 years 23 days ago
Dynamic multi phase scheduling for heterogeneous clusters
Distributed computing systems are a viable and less expensive alternative to parallel computers. However, concurrent programming methods in distributed systems have not been studi...
Florina M. Ciorba, Theodore Andronikos, Ioannis Ri...
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
16 years 23 days ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
16 years 23 days ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
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