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» A high performance JPEG2000 architecture
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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
16 years 2 days ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 10 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
ICWS
2010
IEEE
15 years 8 months ago
Highly Scalable Web Service Composition Using Binary Tree-Based Parallelization
Data intensive applications, e.g. in life sciences, pose new efficiency challenges to the service composition problem. Since today computing power is mainly increased by multiplica...
Patrick Hennig, Wolf-Tilo Balke
AHS
2007
IEEE
215views Hardware» more  AHS 2007»
15 years 6 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
16 years 14 days ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...