2209 search results - page 97 / 442 » A high performance JPEG2000 architecture |
173
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
169
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BSN
2009
IEEE
16 years 1 months ago
2009
IEEE
Wireless systems that form a body-area network must be made small and low power without sacrificing performance. To achieve high-throughput communication in low-cost wireless bod...
151
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ACSAC
2000
IEEE
15 years 11 months ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
159
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CORR
2006
Springer
15 years 6 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
197
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CCGRID
2005
IEEE
16 years 2 days ago
2005
IEEE
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...