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» A high performance JPEG2000 architecture
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ICASSP
2008
IEEE
16 years 27 days ago
Nonlinear residual acoustic echo suppression for high levels of harmonic distortion
Linear adaptive filters are often used for Acoustic Echo Cancellation (AEC) but sometimes fail to perform well in notebook computers and inexpensive telephony devices. Low-qualit...
Diego A. Bendersky, Jack W. Stokes, Henrique S. Ma...
HPCC
2007
Springer
16 years 18 days ago
A Block JRS Algorithm for Highly Parallel Computation of SVDs
This paper presents a new algorithm for computing the singular value decomposition (SVD) on multilevel memory hierarchy architectures. This algorithm is based on one-sided JRS iter...
Mostafa I. Soliman, Sanguthevar Rajasekaran, Reda ...
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 1 days ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
IPPS
2000
IEEE
15 years 10 months ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou
ICIAP
2009
ACM
16 years 7 months ago
Connected Component Labeling Techniques on Modern Architectures
In this paper we present an overview of the historical evolution of connected component labeling algorithms, and in particular the ones applied on images stored in raster scan orde...
Costantino Grana, Daniele Borghesani, Rita Cucchia...