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DAC
2011
ACM
14 years 6 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
IPPS
2006
IEEE
16 years 11 days ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
CSREAESA
2006
15 years 7 months ago
An Efficient Design of High Speed Network Security Platform using Network Processor
: The explosive growth of internet traffic and the increasing complexity of the functions performed by network nodes have given rise to a new breed of programmable micro-processors...
Yong-Sung Jeon, Sang-Woo Lee, Ki-Young Kim
CONNECTION
2006
101views more  CONNECTION 2006»
15 years 6 months ago
High capacity, small world associative memory models
Models of associative memory usually have full connectivity or if diluted, random symmetric connectivity. In contrast, biological neural systems have predominantly local, non-symm...
Neil Davey, Lee Calcraft, Rod Adams
COMCOM
2006
115views more  COMCOM 2006»
15 years 6 months ago
Energy-efficient scheduling and hybrid communication architecture for underwater littoral surveillance
There exists a high demand for reliable, high capacity underwater acoustic networks to allow efficient data gathering and information exchange. This is evidenced by significant re...
Mihaela Cardei