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» A high performance JPEG2000 architecture
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HPCA
2008
IEEE
16 years 1 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
AAECC
2007
Springer
111views Algorithms» more  AAECC 2007»
15 years 6 months ago
When cache blocking of sparse matrix vector multiply works and why
Abstract. We present new performance models and a new, more compact data structure for cache blocking when applied to the sparse matrixvector multiply (SpM×V) operation, y ← y +...
Rajesh Nishtala, Richard W. Vuduc, James Demmel, K...
TPDS
2002
198views more  TPDS 2002»
15 years 6 months ago
Orthogonal Striping and Mirroring in Distributed RAID for I/O-Centric Cluster Computing
This paper presents a new distributed disk-array architecture for achieving high I/O performance in scalable cluster computing. In a serverless cluster of computers, all distribute...
Kai Hwang, Hai Jin, Roy S. C. Ho
DBSEC
2011
245views Database» more  DBSEC 2011»
14 years 10 months ago
Multilevel Secure Data Stream Processing
Abstract. With sensors and mobile devices becoming ubiquitous, situation monitoring applications are becoming a reality. Data Stream Management Systems (DSMSs) have been proposed t...
Raman Adaikkalavan, Indrakshi Ray, Xing Xie
CSE
2011
IEEE
14 years 6 months ago
Parallel Execution of AES-CTR Algorithm Using Extended Block Size
—Data encryption and decryption are common operations in a network based application programs with security. In order to keep pace with the input data rate in such applications, ...
Nhat-Phuong Tran, Myungho Lee, Sugwon Hong, Seung-...