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» A high performance JPEG2000 architecture
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DATE
2006
IEEE
120views Hardware» more  DATE 2006»
16 years 21 days ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
ASAP
2005
IEEE
118views Hardware» more  ASAP 2005»
16 years 8 days ago
Real-time H/W Implementation of the Approximate Discrete Radon Transform
The Radon transform (RT) is a widely studied algorithm used to perform image pattern extraction in fields such as computer graphics, medical imagery, and avionics. Real-time impl...
Michael T. Frederick, Nathan A. VanderHorn, Arun K...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
15 years 8 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
DAC
1997
ACM
15 years 10 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
DAC
1994
ACM
15 years 10 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu