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» A high performance JPEG2000 architecture
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FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 11 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
PROCEDIA
2010
148views more  PROCEDIA 2010»
15 years 1 months ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman
ICPP
2009
IEEE
16 years 1 months ago
Perfomance Models for Blocked Sparse Matrix-Vector Multiplication Kernels
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
FPL
2006
Springer
135views Hardware» more  FPL 2006»
15 years 10 months ago
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
Luis G. Barbero, John S. Thompson
MMS
2002
15 years 6 months ago
An integrated runtime QoS-aware middleware framework for distributed multimedia applications
Abstract. Future-generation distributed multimedia applications are expected to be highly scalable to a wide variety of heterogeneous devices, and highly adaptive across widearea d...
Baochun Li, Dongyan Xu, Klara Nahrstedt