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» A high performance JPEG2000 architecture
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CODES
2008
IEEE
15 years 8 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
JCM
2008
118views more  JCM 2008»
15 years 6 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
EUROPAR
1999
Springer
15 years 11 months ago
Consequences of Modern Hardware Design for Numerical Simulations and Their Realization in FEAST
This paper deals with the influence of hardware aspects of modern computer architectures to the design of software for numerical simulations. We present performance tests for vari...
Christian Becker, Susanne Kilian, Stefan Turek
ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
16 years 3 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
176
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FPL
2004
Springer
128views Hardware» more  FPL 2004»
16 years 6 hour ago
Design and Implementation of a CFAR Processor for Target Detection
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
Cesar Torres-Huitzil, René Cumplido-Parra, ...