Sciweavers

2209 search results - page 183 / 442
» A high performance JPEG2000 architecture
Sort
View
IPPS
2007
IEEE
16 years 27 days ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
CSMR
2004
IEEE
15 years 10 months ago
Supporting Architectural Restructuring by Analyzing Feature Models
In order to lower the risk, reengineering projects aim at high reuse rates. Therefore, tasks like architectural restructuring have to be performed in a way that developed new syst...
Ilian Pashov, Matthias Riebisch, Ilka Philippow
194
Voted
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 11 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
DAC
1997
ACM
15 years 10 months ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
15 years 8 months ago
A 0.4-V UWB baseband processor
A 0.4-V UWB digital baseband processor has been fabricated in a standard-VT 90-nm CMOS technology. The baseband processor operates at an ultra-low supply voltage to reduce energy ...
Vivienne Sze, Anantha P. Chandrakasan