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» A high performance JPEG2000 architecture
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HPCA
2008
IEEE
16 years 7 months ago
Branch-mispredict level parallelism (BLP) for control independence
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin...
CCGRID
2001
IEEE
15 years 10 months ago
OVM: Out-of-Order Execution Parallel Virtual Machine
High performance computing on parallel architectures currently uses different approaches depending on the hardory model of the architecture, the abstraction level of the programmi...
George Bosilca, Gilles Fedak, Franck Cappello
ASWEC
2007
IEEE
15 years 10 months ago
Explicitly Controlling the Fair Service for Busy Web Servers
There is a growing demand for web applications to provide fair service to the highly concurrent requests. In this paper, we present an approach to addressing this requirement. Bas...
Zhanwen Li, David Levy, Shiping Chen, John Zic
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
13 years 9 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 7 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...