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ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
CIBCB
2007
IEEE
15 years 10 months ago
Hybrid Architecture for Accelerating DNA Codeword Library Searching
-- A large and reliable DNA codeword library is the key to the success of DNA based computing. Searching for the set of reliable DNA codewords is an NP-hard problem, which can take...
Qinru Qiu, Daniel J. Burns, Qing Wu, Prakash Mukre
IDA
2009
Springer
16 years 1 months ago
Selecting Computer Architectures by Means of Control-Flow-Graph Mining
Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
Frank Eichinger, Klemens Böhm
DSN
2006
IEEE
16 years 17 days ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
IPPS
2006
IEEE
16 years 16 days ago
Design and analysis of matching circuit architectures for a closest match lookup
— This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a sea...
Kieran McLaughlin, Friederich Kupzog, Holger Blume...