2209 search results - page 135 / 442 » A high performance JPEG2000 architecture |
156
click to vote
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
169
click to vote
HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
166
click to vote
ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
156
click to vote
ICASSP
2011
IEEE
14 years 10 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
150
click to vote
ROBOCUP
2001
Springer
15 years 11 months ago
2001
Springer
Abstract. This paper describes a highly modular hierarchical behaviorbased control system for robots. Key features of the architecture include: easy addition/removal of behaviors, ...