2209 search results - page 131 / 442 » A high performance JPEG2000 architecture |
208
click to vote
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
16 years 1 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
177
click to vote
GLVLSI
2000
IEEE
15 years 11 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
157
click to vote
GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
180
click to vote
FPGA
2000
ACM
15 years 10 months ago
2000
ACM
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
166
click to vote
ISCAS
2005
IEEE
16 years 3 days ago
2005
IEEE
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...