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» A high performance JPEG2000 architecture
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ECBS
1999
IEEE
138views Hardware» more  ECBS 1999»
15 years 10 months ago
Multi-Domain Surety Modeling and Analysis for High Assurance Systems
Engineering systems are becoming increasingly complex as state of the art technologies are incorporated into designs. Surety modeling and analysis is an emerging science which per...
James Davis, Jason Scott, Janos Sztipanovits, Marc...
ANCS
2009
ACM
15 years 4 months ago
An adaptive hash-based multilayer scheduler for L7-filter on a highly threaded hierarchical multi-core server
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs. Previous work has s...
Danhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin L...
SC
2000
ACM
15 years 11 months ago
A Comparative Study of the NAS MG Benchmark across Parallel Languages and Architectures
Hierarchical algorithms such as multigrid applications form an important cornerstone for scientific computing. In this study, we take a first step toward evaluating parallel lan...
Bradford L. Chamberlain, Steven J. Deitz, Lawrence...
AGENTS
1997
Springer
15 years 10 months ago
High-Level Planning and Low-Level Execution: Towards a Complete Robotic Agent
We have been developing Rogue, an architecture that integrates high-level planning with a low-level executing robotic agent. Rogue is designed as the oce gofer task planner for X...
Karen Zita Haigh, Manuela M. Veloso
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
15 years 8 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson