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» A functional formalization of on chip communications
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INFOCOM
2010
IEEE
15 years 4 months ago
On Scheduling for Minimizing End-to-End Buffer Usage over Multihop Wireless Networks
—While there has been much progress in designing backpressure based stabilizing algorithms for multihop wireless networks, end-to-end performance (e.g., end-to-end buffer usage) ...
V. J. Venkataramanan, Xiaojun Lin, Lei Ying, Sanja...
HOTI
2008
IEEE
16 years 19 days ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
16 years 13 days ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
CCS
2007
ACM
16 years 10 days ago
Hardware-rooted trust for secure key management and transient trust
We propose minimalist new hardware additions to a microprocessor chip that protect cryptographic keys in portable computing devices which are used in the field but owned by a cen...
Jeffrey S. Dwoskin, Ruby B. Lee
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 5 days ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...