We develop the scheme of indefinite constraint databases using first-order logic as our representation language. When this scheme is instantiated with temporal constraints, the res...
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
We present a new approach for mapping natural language sentences to their formal meaning representations using stringkernel-based classifiers. Our system learns these classifiers ...
We review the DEVS modeling and simulation framework Its fundamental concepts are discussed from the standpoint of discrete event information processing with an example drawn from...
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...