This paper presents a formal language for the design of component-based enterprise system. The language (StAC) allows the usual parallel and sequential behaviours, but most signifi...
The quality of formal specifications and the circuits they are written for can be evaluated through checks such as vacuity and coverage. Both checks involve mutations to the specif...
In this paper, we present a methodology to express, in a formal way, the requirements of products belonging to a product line. We relied on a formalism allowing the representation ...
Alessandro Fantechi, Stefania Gnesi, Giuseppe Lami...
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...
Abstract: The work presented in this article generalizes the modeling of task scheduling problems with sequence dependent setup time on the basis of task scheduling on single respe...