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HPCA
2008
IEEE
16 years 7 months ago
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
Philip M. Wells, Gurindar S. Sohi
HPCA
2008
IEEE
16 years 7 months ago
CMP network-on-chip overlaid with multi-band RF-interconnect
In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on...
M. Frank Chang, Jason Cong, Adam Kaplan, Mishali N...
HPCA
2007
IEEE
16 years 7 months ago
A Burst Scheduling Access Reordering Mechanism
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
Jun Shao, Brian T. Davis
HPCA
2007
IEEE
16 years 7 months ago
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
Stijn Eyerman, Lieven Eeckhout
HPCA
2007
IEEE
16 years 7 months ago
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...
Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Pa...