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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
16 years 28 days ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
GLOBECOM
2006
IEEE
16 years 28 days ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
IEEEPACT
2006
IEEE
16 years 27 days ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
HPCA
2005
IEEE
16 years 15 days ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ICPADS
2005
IEEE
16 years 14 days ago
A Differentiated Message Delivery Architecture to Control Spam
Unsolicited bulk electronic mail (spam) is increasingly plaguing the Internet Email system and deteriorating its value as a convenient communication tools. In this paper we argue ...
Zhenhai Duan, Yingfei Dong, Kartik Gopalan