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HPCC
2009
Springer
15 years 11 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
IEEEPACT
1998
IEEE
15 years 11 months ago
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP)...
Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, J...
IPPS
1994
IEEE
15 years 11 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
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IPPS
1998
IEEE
15 years 10 months ago
Comparing the Optimal Performance of Different MIMD Multiprocessor Architectures
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...
Lars Lundberg, Håkan Lennerstad
MIDDLEWARE
2000
Springer
15 years 10 months ago
The Role of Software Architecture in Constraining Adaptation in Component-Based Middleware Platforms
Future middleware platforms will need to be more configurable in order to meet the demands of a wide variety of application domains. Furthermore, we believe that such platforms wil...
Gordon S. Blair, Lynne Blair, Valérie Issar...