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HPCA
2008
IEEE
16 years 6 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
HPCA
2008
IEEE
16 years 6 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
HPCA
2008
IEEE
16 years 6 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
HPCA
2008
IEEE
16 years 6 months ago
Amdahl's Law in the multicore era
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
Mark D. Hill
HPCA
2008
IEEE
16 years 6 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
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