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CASES
2009
ACM
16 years 1 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
CASES
2009
ACM
16 years 1 months ago
Towards scalable reliability frameworks for error prone CMPs
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
Joseph Sloan, Rakesh Kumar
SIGCOMM
2009
ACM
16 years 1 months ago
Crossbow: a vertically integrated QoS stack
This paper describes a new architecture which addresses Quality of Service (QoS) by creating unique flows for applications, services, or subnets. A flow is a dedicated and indep...
Sunay Tripathi, Nicolas Droux, Thirumalai Srinivas...
IEEEPACT
2008
IEEE
16 years 27 days ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
CLUSTER
2007
IEEE
16 years 25 days ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
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