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HPCA
2008
IEEE
16 years 1 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
HPCA
2008
IEEE
16 years 1 months ago
Prediction of CPU idle-busy activity pattern
Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and h...
Qian Diao, Justin J. Song
160
Voted
ICCAD
2008
IEEE
129views Hardware» more  ICCAD 2008»
16 years 1 months ago
Path-RO: a novel on-chip critical path delay measurement under process variations
— As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actua...
Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Dat...
ISORC
2008
IEEE
16 years 1 months ago
Hardware Objects for Java
Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled ...
Martin Schoeberl, Christian Thalinger, Stephan Kor...
ITNG
2008
IEEE
16 years 1 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
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