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ERSA
2008
185views Hardware» more  ERSA 2008»
15 years 7 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
SCOPES
2005
Springer
15 years 11 months ago
Software Synthesis from the Dataflow Interchange Format
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...
Chia-Jui Hsu, Shuvra S. Bhattacharyya
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
16 years 2 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 9 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ECCV
2010
Springer
15 years 6 months ago
Superpixels and Supervoxels in an Energy Optimization Framework
Many methods for object recognition, segmentation, etc., rely on tessellation of an image into "superpixels". A superpixel is an image patch which is better aligned with ...
Olga Veksler, Yuri Boykov, Paria Mehrani