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DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 12 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
15 years 11 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
15 years 11 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
CHI
1999
ACM
15 years 11 months ago
Cooperative Inquiry: Developing new Technologies for Children with Children
In today’s homes and schools, children are emerging as frequent and experienced users of technology [3, 14]. As this trend continues, it becomes increasingly important to ask if...
Allison Druin
SIGMOD
1999
ACM
114views Database» more  SIGMOD 1999»
15 years 11 months ago
A Layered Architecture for Querying Dynamic Web Content
The design of webbases, database systems for supporting Webbased applications, is currently an active area of research. In this paper, we propose a 3-layer architecture for design...
Hasan Davulcu, Juliana Freire, Michael Kifer, I. V...