100 search results - page 17 / 20 » A decoupled KILO-instruction processor |
156
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ISCA
1999
IEEE
15 years 10 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
141
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ISCA
2008
IEEE
16 years 10 days ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
178
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ISCA
2003
IEEE
15 years 11 months ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
180
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CODES
2007
IEEE
16 years 8 days ago
2007
IEEE
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
147
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SIGMOD
2010
ACM
15 years 10 months ago
2010
ACM
We present SecureBlox, a declarative system that unifies a distributed query processor with a security policy framework. SecureBlox decouples security concerns from system speci...