536 search results - page 46 / 108 » A computer verified, monadic, functional implementation of t... |
142
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VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
170
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DAC
1989
ACM
15 years 9 months ago
1989
ACM
We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the cond...
131
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DAC
1998
ACM
15 years 10 months ago
1998
ACM
We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthe...
183
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CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
134
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...