1855 search results - page 280 / 371 » A coding theorem for distributed computation |
171
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
161
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
172
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HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
Most of the prediction mechanisms predict a single path to continue the execution on a branch. Alternatively, we may exploit parallelism from either possible paths of a branch, di...
162
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HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
159
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IEEEPACT
1998
IEEE
15 years 10 months ago
1998
IEEE
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...