1008 search results - page 92 / 202 » A cis-regulatory logic simulator |
179
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
147
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VTS
2006
IEEE
16 years 9 days ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
155
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
150
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MSE
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a PC based software running on PC dedicated to the training in sub-micron CMOS VLSI design. The software firstly consists in a HDL-based schematic editor with ...
161
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...