1008 search results - page 85 / 202 » A cis-regulatory logic simulator |
150
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JOLPE
2010
15 years 4 months ago
2010
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
182
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MEMOCODE
2010
IEEE
15 years 4 months ago
2010
IEEE
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
204
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CDC
2010
IEEE
15 years 1 months ago
2010
IEEE
In this paper we address the problem of physical node capture attacks in wireless sensor networks and provide a control theoretic framework to model physical node capture, cloned n...
173
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SIGSOFT
2010
ACM
15 years 1 months ago
2010
ACM
This presentation demonstrates the early results from the French ANR project RT-Simex. RT-Simex proposes a set of tools to analyze timing of parallel embedded code and trace the s...
169
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...