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ISMVL
1994
IEEE
98views Hardware» more  ISMVL 1994»
15 years 10 months ago
Digital Circuit Verification Using Partially-Ordered State Models
Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over "weakened" state values. This technique has long been practice...
Carl-Johan H. Seger, Randal E. Bryant
TMC
2012
13 years 8 months ago
Protecting Location Privacy in Sensor Networks against a Global Eavesdropper
— While many protocols for sensor network security provide confidentiality for the content of messages, contextual information usually remains exposed. Such information can be c...
Kiran Mehta, Donggang Liu, Matthew Wright
CONCUR
2003
Springer
15 years 11 months ago
Comparative Branching-Time Semantics
d Abstract) Christel Baier1 , Holger Hermanns2,3 , Joost-Pieter Katoen2 , and Verena Wolf1 1 Institut f¨ur Informatik I, University of Bonn R¨omerstraße 164, D-53117 Bonn, Germa...
Christel Baier, Holger Hermanns, Joost-Pieter Kato...
INFOCOM
2009
IEEE
16 years 28 days ago
Circuits/Cutsets Duality and a Unified Algorithmic Framework for Survivable Logical Topology Design in IP-over-WDM Optical Netwo
: Given a logical topology and a physical topology , the survivable logical topology design problem in an IP-overWDM optical network is to map the logical links into lightpaths in ...
Krishnaiyan Thulasiraman, Muhammad S. Javed, Guoli...
DAC
2005
ACM
16 years 7 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...