1008 search results - page 46 / 202 » A cis-regulatory logic simulator |
160
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APCCAS
2006
IEEE
16 years 6 days ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
144
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PATMOS
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
150
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PDP
1997
IEEE
15 years 10 months ago
1997
IEEE
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
159
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IJSYSC
2006
15 years 6 months ago
2006
: A backlash compensator is designed for nonlinear systems using the fuzzy logic. The classification property of fuzzy logic systems makes them a natural candidate for the rejectio...
179
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CHES
2009
Springer
16 years 28 days ago
2009
Springer
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...