1008 search results - page 114 / 202 » A cis-regulatory logic simulator |
186
click to vote
ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
195
click to vote
DFT
2008
IEEE
16 years 23 days ago
2008
IEEE
Tolerating defects and fabrication variations will be critical in any system made with devices that have nanometer feature sizes. This paper considers how fabrication variations a...
133
click to vote
ASPDAC
2005
ACM
15 years 12 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
160
click to vote
GW
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. We present an collaborative approach towards a detailed understanding of the usage of pointing gestures accompanying referring expressions. This effort is undertaken in t...
151
click to vote
AMAST
2004
Springer
15 years 11 months ago
2004
Springer
JavaFAN uses a Maude rewriting logic specification of the JVM semantics as the basis of a software analysis tool with competitive performance. It supports formal analysis of concu...