1008 search results - page 111 / 202 » A cis-regulatory logic simulator |
157
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PATMOS
2005
Springer
15 years 11 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
161
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CHES
2004
Springer
15 years 11 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
162
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AGP
2003
IEEE
15 years 11 months ago
2003
IEEE
In ordered logic programs, i.e. partially ordered sets of clauses where smaller rules carry more preference, inconsistencies, which appear as conflicts between applicable rules, a...
169
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
194
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...