1008 search results - page 103 / 202 » A cis-regulatory logic simulator |
167
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TVLSI
2010
15 years 1 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
178
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ISQED
2011
IEEE
14 years 10 months ago
2011
IEEE
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the microprocesso...
162
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CN
2011
14 years 10 months ago
2011
We provide a design of a control and management plane for data networks using the abstraction of 4D architecture, utilizing and extending 4D’s concept of a logically centralized...
144
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
137
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DDECS
2009
IEEE
16 years 1 months ago
2009
IEEE
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...