228 search results - page 5 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
154
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GLVLSI
2010
IEEE
15 years 11 months ago
2010
IEEE
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
123
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ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
145
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ISLPED
2009
ACM
16 years 17 days ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
159
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ASPDAC
2010
ACM
15 years 4 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
173
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...