228 search results - page 18 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
170
Voted
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
144
Voted
DAC
1999
ACM
16 years 7 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
129
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
162
click to vote
ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
160
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CASES
2008
ACM
15 years 8 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...