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» A Verification Methodology for Model Fields
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DAC
1996
ACM
15 years 10 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
CAV
2001
Springer
87views Hardware» more  CAV 2001»
15 years 9 months ago
Microarchitecture Verification by Compositional Model Checking
Compositional model checking is used to verify a processor microarchitecture containing most of the features of a modern microprocessor, including branch prediction, speculative ex...
Ranjit Jhala, Kenneth L. McMillan
DAC
2008
ACM
16 years 6 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
ICSEA
2008
IEEE
16 years 9 days ago
A UML Based Methodology to Ease the Modeling of a Set of Related Systems
Despite progress in model engineering, modeling large distributed systems is still a long and complex task. This paper outlines a methodology based on UML to make the modeling of ...
Firas Alhalabi, Mathieu Maranzana, Jean-Louis Sour...
DEXAW
1999
IEEE
94views Database» more  DEXAW 1999»
15 years 10 months ago
Reuse, Validation and Verification of System Development Processes
The wide variety of abstract system development methodologies available includes the waterfall and V models. These models are often too generic and need careful adaptation to suit ...
Peter J. Funk, Ivica Crnkovic