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» A VHDL-based bus model for multi-PCB system design
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ATVA
2005
Springer
111views Hardware» more  ATVA 2005»
15 years 11 months ago
Model Checking Prioritized Timed Automata
Abstract. Priorities are often used to resolve conflicts in timed systems. However, priorities are not directly supported by state-of-art model checkers. Often, a designer has to ...
Shang-Wei Lin, Pao-Ann Hsiung, Chun-Hsian Huang, Y...
CODES
2004
IEEE
15 years 9 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CASES
2003
ACM
15 years 11 months ago
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
Ramnath Venugopalan, Prasanth Ganesan, Pushkin Ped...
SEUS
2008
IEEE
16 years 11 days ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic
PPL
2008
185views more  PPL 2008»
15 years 6 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...