3955 search results - page 699 / 791 » A Transactional Architecture for Simulation |
152
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IPPS
2007
IEEE
16 years 20 days ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
175
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GECCO
2007
Springer
16 years 15 days ago
2007
Springer
Design, development and evaluation of adaptive, scalable, and power aware Bio/Nature inspired routing protocols has received a significant amount of attention in the recent past....
173
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ICS
2007
Tsinghua U.
16 years 15 days ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
163
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DATE
2006
IEEE
16 years 12 days ago
2006
IEEE
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
154
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GLOBECOM
2006
IEEE
16 years 12 days ago
2006
IEEE
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...